The SensBench Geek Lab pathway is for makers who already read datasheets for fun: logic analysis, long-range radio, custom simulated chips, and toolchain-grade automation through MCP.

Signal-level work

The Logic Analyzer Rig turns an ESP32 into an 8-channel sniffer. Simulate the capture in the browser first, then run it on the bench — timing budgets verified before hardware. Pair it with the KB’s GPIO timing guides.

Long-range radio

The LoRa Long-Range Node pairs SX1276 link-budget examples with a simulated radio path, so RSSI and SNR trade-offs are explored where the trial loop is seconds — not field trips.

Automate the toolchain

Wire the SensBench MCP server into Claude Code or Cursor: compile Arduino and ESP-IDF projects, convert Wokwi diagrams, and iterate firmware from your terminal. The custom chips tutorial shows how far the simulator’s component model goes.

FAQs

Can I bring my own libraries? Yes — cloud builds resolve your component list like a local workspace.

Is there a build quota? Free tier includes one compile per day; credits and Maker/Pro plans raise it.

Which boards are simulated? ESP32 family, Pi Pico and an expanding set — see the simulator overview.